`timescale 1ns/1ns module sequence_detect( input clk, input rst_n, input data, output reg match, output reg not_match ); localparam S0 = 2'b00; localparam S1 = 2'b01; localparam S2 = 2'b10; reg [2:0] counter; reg [1:0] s,ns; reg [4:0] data_tmp; always@(posedge clk or negedge rst_n)beg...