`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);
	localparam S0 = 2'b00;
	localparam S1 = 2'b01;
	localparam S2 = 2'b10;

	reg [2:0] counter;
	reg [1:0] s,ns;
	reg [4:0] data_tmp;

	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)counter <= 'd0;
		else if(counter == 3'b101)
		counter <= 'd0;
		else
		counter <= counter + 1'b1;
	end

	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)data_tmp <='d0;
		else begin
			case(counter)
			0:data_tmp[0] = data;
			1:data_tmp[1] = data;
			2:data_tmp[2] = data;
			3:data_tmp[3] = data;
			4:data_tmp[4] = data;
			endcase
		end
	end
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)s <= S0;
		else
			s <= ns;
	end

	always@(*)begin
		case(s)
		S0:ns=S1;
		S1:ns=(counter=='d5)?S2:S1;
		S2:ns=S1;
		default:ns=S0;
		endcase
	end

	always@(*)begin
		if(!rst_n)match<='d0;
		else if((s==S2)&&(data==1'b0)&&(data_tmp==5'b01110))
		match <= 'b1;
		else
		match <= 'b0;
	end

	always@(*)begin
		if(!rst_n)not_match<='d0;
		else if((s==S2)&&(data==1'b1))
		not_match <= 'b1;
		else
		not_match <= 'b0;
	end
endmodule

兩段式狀態(tài)機(jī)

三個(gè)狀態(tài)：

s0：等待輸入

s1：輸入中

s2：判斷