`timescale 1ns/1ns

module lca_4(
	input		[3:0]       A_in  ,
	input	    [3:0]		B_in  ,
    input                   C_1   ,
 
 	output	 wire			CO    ,
	output   wire [3:0]	    S
);

    wire [3:0] C;
    wire [4:0] c_temp;
    // assign S[0] = A_in[0] ^ B_in[0] ^ C_1;
    // assign S[1] = A_in[1] ^ B_in[1] ^ C[0];
    // assign S[2] = A_in[2] ^ B_in[2] ^ C[1];
    // assign S[3] = A_in[3] ^ B_in[3] ^ C[2];
	assign S = P ^ c_temp;
	assign c_temp = {C,C_1};
	wire [3:0] G,P;
	assign G = A_in & B_in;
	assign P = A_in ^ B_in;
	generate
		genvar i;
		for( i = 0 ; i < 4; i = i + 1)begin:for_c
			assign C[i] = G[i] || P[i] & c_temp[i];
		end
	endgenerate
    // assign C[0] = (A_in[0] & B_in[0]) || ((A_in[0] ^ B_in[0]) & C_1);
    // assign C[1] = (A_in[1] & B_in[1]) || ((A_in[1] ^ B_in[1]) & C[0]);
    // assign C[2] = (A_in[2] & B_in[2]) || ((A_in[2] ^ B_in[2]) & C[1]);
    // assign C[3] = (A_in[3] & B_in[3]) || ((A_in[3] ^ B_in[3]) & C[2]);
    assign CO = C[3];
endmodule