`timescale 1ns/1ns

module even_div
    (
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out2,
    output    wire clk_out4,
    output    wire clk_out8
    );
//*************code***********//
reg [2:0]cnt;
reg clk_out2_reg,clk_out4_reg,clk_out8_reg;
always@(posedge clk_in or negedge rst)begin
    if(!rst)cnt<=0;
    else if(cnt==3'd7) cnt<=0;
    else  cnt<=cnt+1;
end
assign clk_out2=clk_out2_reg;
assign clk_out4=clk_out4_reg;
assign clk_out8=clk_out8_reg;

always@(posedge clk_in or negedge rst)begin
    if(!rst) clk_out2_reg<=0;
    else begin
        if(cnt==0)clk_out2_reg<=1;
        else      clk_out2_reg<=~clk_out2_reg;
    end
end
always@(posedge clk_in or negedge rst)begin
    if(!rst) clk_out4_reg<=0;
    else begin
        if(cnt==0)clk_out4_reg<=1;
        else  if(cnt==3'd2 |cnt==3'd4 |cnt==3'd6)    clk_out4_reg<=~clk_out4_reg;
        else  clk_out4_reg<=clk_out4_reg;
    end
end
always@(posedge clk_in or negedge rst)begin
    if(!rst) clk_out8_reg<=0;
    else begin
        if(cnt==0)clk_out8_reg<=1;
        else   if(cnt==3'd4)   clk_out8_reg<=~clk_out8_reg;
        else   clk_out8_reg<=clk_out8_reg;
    end
end
//*************code***********//
endmodule