`timescale 1ns/1ns

module div_M_N(
 input  wire clk_in,
 input  wire rst,
 output wire clk_out
);
parameter M_N = 8'd87; 
parameter c89 = 8'd24; // 8/9時鐘切換點
parameter div_e = 5'd8; //偶數(shù)周期
parameter div_o = 5'd9; //奇數(shù)周期

//之前得奇數(shù)分頻要求了占空比50%,所以牽扯到下降沿，現(xiàn)在這個未要求占空比，用clk_in上升沿即可,9分配1 4個 0 5個
reg [7:0]cnt;
reg [3:0]cnt_8,cnt_9;
always@(posedge clk_in or negedge rst)begin
    if(!rst)begin
        cnt <= 8'b0;
    end
    else if(cnt < M_N)begin
        cnt <= cnt + 1'b1;
    end
    else begin
        cnt <= 8'd1;
    end
end
//cnt8
always@(posedge clk_in or negedge rst)begin
    if(!rst)begin
        cnt_8 <= 4'b0;
    end
    else if(cnt <= c89)begin
        if(cnt_8 == 4'd8)begin
            cnt_8 <= 4'd1;
        end
        else begin
            cnt_8 <= cnt_8 + 1'b1;
        end
    end
    else if(cnt == M_N)begin
        cnt_8 <= 4'd1;
    end
end
//cnt9
always@(posedge clk_in or negedge rst)begin
    if(!rst)begin
        cnt_9 <= 4'b0;
    end
    else if(cnt >= c89 && cnt < M_N)begin 
        if(cnt_9 == 4'd9)begin
            cnt_9 <= 4'd1;
        end
        else begin
            cnt_9 <= cnt_9 + 1'b1;
        end
    end
    else if(cnt == M_N)begin
        cnt_9 <= 4'b0;
    end

end


reg clk_out_temp;
always@(posedge clk_in or negedge rst)begin
    if(!rst)begin
        clk_out_temp <= 1'b0;
    end
    else if(cnt <= c89)begin //3個8分頻
        if(cnt_8 == 4'd0 | cnt_8 == 4'd8)begin
            clk_out_temp <= 1'b1;
        end
        else if(cnt_8 == 4'd4)begin
            clk_out_temp <= 1'b0;
        end
    end
    else if(cnt > c89 && cnt <= M_N) begin  //7個9分頻
        if(cnt_9 == 4'd0 | cnt_9 == 4'd9)begin
            clk_out_temp <= 1'b1;
        end
        else if(cnt_9 == 4'd4)begin
            clk_out_temp <= 1'b0;
        end
    end
end

assign clk_out = clk_out_temp;
endmodule